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<div class="textblock"><code>#include &quot;uvm_macros.svh&quot;</code><br />
<code>#include &quot;<a class="el" href="axi__if__abstract_8svh_source.html">axi_if_abstract.svh</a>&quot;</code><br />
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<p><a href="axi__pkg_8sv_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
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Classes</h2></td></tr>
<tr class="memitem:structaxi__seq__item__aw__vector__s"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__aw__vector__s">axi_seq_item_aw_vector_s</a></td></tr>
<tr class="memdesc:structaxi__seq__item__aw__vector__s"><td class="mdescLeft">&#160;</td><td class="mdescRight">This packed struct is used to send write address channel information between the DUT and TB.  <a href="axi__pkg_8sv.html#structaxi__seq__item__aw__vector__s">More...</a><br /></td></tr>
<tr class="separator:structaxi__seq__item__aw__vector__s"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structaxi__seq__item__w__vector__s"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__w__vector__s">axi_seq_item_w_vector_s</a></td></tr>
<tr class="memdesc:structaxi__seq__item__w__vector__s"><td class="mdescLeft">&#160;</td><td class="mdescRight">This packed struct is used to send write data channel information between the DUT and TB.  <a href="axi__pkg_8sv.html#structaxi__seq__item__w__vector__s">More...</a><br /></td></tr>
<tr class="separator:structaxi__seq__item__w__vector__s"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structaxi__seq__item__b__vector__s"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__b__vector__s">axi_seq_item_b_vector_s</a></td></tr>
<tr class="memdesc:structaxi__seq__item__b__vector__s"><td class="mdescLeft">&#160;</td><td class="mdescRight">This packed struct is used to send write response channel information between the DUT and TB.  <a href="axi__pkg_8sv.html#structaxi__seq__item__b__vector__s">More...</a><br /></td></tr>
<tr class="separator:structaxi__seq__item__b__vector__s"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structaxi__seq__item__ar__vector__s"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__ar__vector__s">axi_seq_item_ar_vector_s</a></td></tr>
<tr class="memdesc:structaxi__seq__item__ar__vector__s"><td class="mdescLeft">&#160;</td><td class="mdescRight">This packed struct is used to send read address channel information between the DUT and TB.  <a href="axi__pkg_8sv.html#structaxi__seq__item__ar__vector__s">More...</a><br /></td></tr>
<tr class="separator:structaxi__seq__item__ar__vector__s"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structaxi__seq__item__r__vector__s"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__r__vector__s">axi_seq_item_r_vector_s</a></td></tr>
<tr class="memdesc:structaxi__seq__item__r__vector__s"><td class="mdescLeft">&#160;</td><td class="mdescRight">This packed struct is used to send read data channel information between the DUT and TB.  <a href="axi__pkg_8sv.html#structaxi__seq__item__r__vector__s">More...</a><br /></td></tr>
<tr class="separator:structaxi__seq__item__r__vector__s"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memitem:namespaceaxi__pkg"><td class="memItemLeft" align="right" valign="top"> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="namespaceaxi__pkg.html">axi_pkg</a></td></tr>
<tr class="memdesc:namespaceaxi__pkg"><td class="mdescLeft">&#160;</td><td class="mdescRight">enums, defines, typedefs needed in AXI <br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
Typedefs</h2></td></tr>
<tr class="memitem:a4c2433056567c2f85987e6a18fef7269"><td class="memItemLeft" align="right" valign="top">typedef bit&lt; <a class="el" href="axi__pkg_8sv.html#a3609a21c67a3c1b8ffe65c66bd413bdc">AXI_SEQ_ITEM_AW_NUM_BITS</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a4c2433056567c2f85987e6a18fef7269">axi_seq_item_aw_vector_t</a></td></tr>
<tr class="memdesc:a4c2433056567c2f85987e6a18fef7269"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit vector containing packed write address channel values.  <a href="#a4c2433056567c2f85987e6a18fef7269">More...</a><br /></td></tr>
<tr class="separator:a4c2433056567c2f85987e6a18fef7269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adde7476f486c8cdd6acc0bb33ef1ea70"><td class="memItemLeft" align="right" valign="top">typedef bit&lt; <a class="el" href="axi__pkg_8sv.html#abcfb4d0ea71d9d468d8d8ee492acdcc7">AXI_SEQ_ITEM_W_NUM_BITS</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#adde7476f486c8cdd6acc0bb33ef1ea70">axi_seq_item_w_vector_t</a></td></tr>
<tr class="memdesc:adde7476f486c8cdd6acc0bb33ef1ea70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit vector containing packed write data channel values.  <a href="#adde7476f486c8cdd6acc0bb33ef1ea70">More...</a><br /></td></tr>
<tr class="separator:adde7476f486c8cdd6acc0bb33ef1ea70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4622f8d1c44a8bc0dd6e8eea04dfcfbb"><td class="memItemLeft" align="right" valign="top">typedef bit&lt; <a class="el" href="axi__pkg_8sv.html#a39ab1b1c2a814941adb3f0ceeef4b2aa">AXI_SEQ_ITEM_B_NUM_BITS</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a4622f8d1c44a8bc0dd6e8eea04dfcfbb">axi_seq_item_b_vector_t</a></td></tr>
<tr class="memdesc:a4622f8d1c44a8bc0dd6e8eea04dfcfbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit vector containing packed write response channel values.  <a href="#a4622f8d1c44a8bc0dd6e8eea04dfcfbb">More...</a><br /></td></tr>
<tr class="separator:a4622f8d1c44a8bc0dd6e8eea04dfcfbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a312fd2db42dcfe2d4cadc9b7175357f0"><td class="memItemLeft" align="right" valign="top">typedef bit&lt; <a class="el" href="axi__pkg_8sv.html#aa8976bdc123c77c1eb4afc1e8f127c53">AXI_SEQ_ITEM_AR_NUM_BITS</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a312fd2db42dcfe2d4cadc9b7175357f0">axi_seq_item_ar_vector_t</a></td></tr>
<tr class="memdesc:a312fd2db42dcfe2d4cadc9b7175357f0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit vector containing packed read address channel values.  <a href="#a312fd2db42dcfe2d4cadc9b7175357f0">More...</a><br /></td></tr>
<tr class="separator:a312fd2db42dcfe2d4cadc9b7175357f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6ff9a9241c4f3bc3a934bdd6c967107f"><td class="memItemLeft" align="right" valign="top">typedef bit&lt; <a class="el" href="axi__pkg_8sv.html#a5ca03583008df77c259a2f1503fb3e9c">AXI_SEQ_ITEM_R_NUM_BITS</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a6ff9a9241c4f3bc3a934bdd6c967107f">axi_seq_item_r_vector_t</a></td></tr>
<tr class="memdesc:a6ff9a9241c4f3bc3a934bdd6c967107f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit vector containing packed read data channel values.  <a href="#a6ff9a9241c4f3bc3a934bdd6c967107f">More...</a><br /></td></tr>
<tr class="separator:a6ff9a9241c4f3bc3a934bdd6c967107f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:a80eb2d0d4b7978e716989546b93fa848"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848">burst_size_t</a> { <br />
&#160;&#160;<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a35e86b0e0f722377718cfd9758cc8deb">e_1BYTE</a> = 0b000, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a3b71b0b1775203dd26093fab08eab521">e_2BYTES</a> = 0b001, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a01afde8339a75426fad830f0962f10e5">e_4BYTES</a> = 0b010, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a7b0e2780221101a2de9ed044008e6e96">e_8BYTES</a> = 0b011, 
<br />
&#160;&#160;<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a98f7ccdf3d33a3e5a07253878d977d83">e_16BYTES</a> = 0b100, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a9abb5c28cb0c40e8845d6470b4e3657c">e_32BYTES</a> = 0b101, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a7abf5855cf6f1865568a9384c9fbe219">e_64BYTES</a> = 0b110, 
<a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848a47e5b2d6b5341c90d3f172d47594f294">e_128BYTES</a> = 0b111
<br />
 }<tr class="memdesc:a80eb2d0d4b7978e716989546b93fa848"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size of beat in bytes. (How many bytes of the data bus are used each beat(clk).  <a href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:a80eb2d0d4b7978e716989546b93fa848"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac948ddb69d517d21ce13ec363f10b95b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95b">burst_type_t</a> { <a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95ba7759f7b1845ad2e729ccf878ff1b2e40">e_FIXED</a> = 0b00, 
<a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95ba66585ba1c5e2c6e635898a45086d9c1d">e_INCR</a> = 0b01, 
<a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95bac6caff421238a869ca419bbd19325b8c">e_WRAP</a> = 0b10, 
<a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95ba4375ed062d322ec2c9581b61f2b6b689">e_RESERVED</a> = 0b11
 }<tr class="memdesc:ac948ddb69d517d21ce13ec363f10b95b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Does the address stay fixed, increment, or wrap during the burst?  <a href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95b">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ac948ddb69d517d21ce13ec363f10b95b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8b0f779dd7c96753c4355a5c86e0f9d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9d">response_type_t</a> { <a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9da01e497eaf63b1bf53a0105479c8c74de">e_OKAY</a> = 0b00, 
<a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9dad43dac468b1bc25183dd4e26a504bc3a">e_EXOKAY</a> = 0b01, 
<a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9da1fe56b6c3532c9dbf95cd6ceb8e6b280">e_SLVERR</a> = 0b10, 
<a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9dafdc0186d85ac39b36e66dab544b906c3">e_DECERR</a> = 0b11
 }<tr class="memdesc:ac8b0f779dd7c96753c4355a5c86e0f9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write response values.  <a href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9d">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ac8b0f779dd7c96753c4355a5c86e0f9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a6c8ade980c77973114ddfd403d25bc23"><td class="memItemLeft" align="right" valign="top">bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a6c8ade980c77973114ddfd403d25bc23">calculate_burst_aligned_address</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; address, input bit&lt; 2:0 &gt; burst_size)</td></tr>
<tr class="memdesc:a6c8ade980c77973114ddfd403d25bc23"><td class="mdescLeft">&#160;</td><td class="mdescRight">calculate burst_size aligned address  <a href="#a6c8ade980c77973114ddfd403d25bc23">More...</a><br /></td></tr>
<tr class="separator:a6c8ade980c77973114ddfd403d25bc23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4af175634a55ae773681009062989a5d"><td class="memItemLeft" align="right" valign="top">bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a4af175634a55ae773681009062989a5d">calculate_bus_aligned_address</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input int bus_size)</td></tr>
<tr class="memdesc:a4af175634a55ae773681009062989a5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">calculate bus-siz aligned address  <a href="#a4af175634a55ae773681009062989a5d">More...</a><br /></td></tr>
<tr class="separator:a4af175634a55ae773681009062989a5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbfbf7a50bf6dabae3804e39d05434b1"><td class="memItemLeft" align="right" valign="top">bit&lt; <a class="el" href="axi__pkg_8sv.html#ab7eed2ef1c0b3f2e73a3ebe25df4b9e6">C_AXI_LEN_WIDTH</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#afbfbf7a50bf6dabae3804e39d05434b1">calculate_axlen</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input bit&lt; 2:0 &gt; burst_size, input shortint burst_length)</td></tr>
<tr class="memdesc:afbfbf7a50bf6dabae3804e39d05434b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">calculate awlen or arlen  <a href="#afbfbf7a50bf6dabae3804e39d05434b1">More...</a><br /></td></tr>
<tr class="separator:afbfbf7a50bf6dabae3804e39d05434b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1bb88ba6ed9a3a081a64f90042a681b5"><td class="memItemLeft" align="right" valign="top">byte&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a1bb88ba6ed9a3a081a64f90042a681b5">calculate_unalignment_offset</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input byte burst_size)</td></tr>
<tr class="memdesc:a1bb88ba6ed9a3a081a64f90042a681b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">calculate how unaligned the address is from the burst size  <a href="#a1bb88ba6ed9a3a081a64f90042a681b5">More...</a><br /></td></tr>
<tr class="separator:a1bb88ba6ed9a3a081a64f90042a681b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1fe6872099e588c0924c5bb71a9964b3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a1fe6872099e588c0924c5bb71a9964b3">calculate_wrap_boundary</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input bit&lt; 2:0 &gt; burst_size, input shortint burst_length, output bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; Lower_Wrap_Boundary, output bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; Upper_Wrap_Boundary)</td></tr>
<tr class="memdesc:a1fe6872099e588c0924c5bb71a9964b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">calculate the wrap boundaries for a given burst  <a href="#a1fe6872099e588c0924c5bb71a9964b3">More...</a><br /></td></tr>
<tr class="separator:a1fe6872099e588c0924c5bb71a9964b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2bdf1895089f5dfc5195f221ecfc02d8"><td class="memItemLeft" align="right" valign="top">bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a2bdf1895089f5dfc5195f221ecfc02d8">get_next_address</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input bit&lt; 2:0 &gt; burst_size, input shortint burst_length, input bit&lt; 1:0 &gt; burst_type, input int beat_cnt, input int lane, input int data_bus_bytes)</td></tr>
<tr class="memdesc:a2bdf1895089f5dfc5195f221ecfc02d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get next address for reading/writing to memory.  <a href="#a2bdf1895089f5dfc5195f221ecfc02d8">More...</a><br /></td></tr>
<tr class="separator:a2bdf1895089f5dfc5195f221ecfc02d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a269e42497226a3a0def0fc1bfdd7d22a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a269e42497226a3a0def0fc1bfdd7d22a">get_beat_N_byte_lanes</a> (input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt; addr, input bit&lt; 2:0 &gt; burst_size, input shortint burst_length, input bit&lt; 1:0 &gt; burst_type, input int beat_cnt, input int data_bus_bytes, output int Lower_Byte_Lane, output int Upper_Byte_Lane, output int offset)</td></tr>
<tr class="memdesc:a269e42497226a3a0def0fc1bfdd7d22a"><td class="mdescLeft">&#160;</td><td class="mdescRight">return byte lanes that contain valid data  <a href="#a269e42497226a3a0def0fc1bfdd7d22a">More...</a><br /></td></tr>
<tr class="separator:a269e42497226a3a0def0fc1bfdd7d22a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
Variables</h2></td></tr>
<tr class="memitem:a150391b59e1b2851c89272c84ed02077"><td class="memItemLeft" align="right" valign="top">parameter&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a> = <a class="el" href="params__pkg_8sv.html#acc3f1524ce307037059dc1777798ee1f">params_pkg::AXI_ID_WIDTH</a></td></tr>
<tr class="separator:a150391b59e1b2851c89272c84ed02077"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3640be56d79c0ba42bea37784ac9ae6d"><td class="memItemLeft" align="right" valign="top">parameter&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a3640be56d79c0ba42bea37784ac9ae6d">C_AXI_DATA_WIDTH</a> = <a class="el" href="params__pkg_8sv.html#aefb87aba63546102696230c367fae534">params_pkg::AXI_DATA_WIDTH</a></td></tr>
<tr class="separator:a3640be56d79c0ba42bea37784ac9ae6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3a4347d855f294afac6e48ad076f677"><td class="memItemLeft" align="right" valign="top">parameter&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a> = <a class="el" href="params__pkg_8sv.html#a243e565e7e0e8614253648f1c4c47a2a">params_pkg::AXI_ADDR_WIDTH</a></td></tr>
<tr class="separator:ab3a4347d855f294afac6e48ad076f677"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7eed2ef1c0b3f2e73a3ebe25df4b9e6"><td class="memItemLeft" align="right" valign="top">parameter&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#ab7eed2ef1c0b3f2e73a3ebe25df4b9e6">C_AXI_LEN_WIDTH</a> = <a class="el" href="params__pkg_8sv.html#afd06121ba6ea9496041ee05853712a73">params_pkg::AXI_LEN_WIDTH</a></td></tr>
<tr class="separator:ab7eed2ef1c0b3f2e73a3ebe25df4b9e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3609a21c67a3c1b8ffe65c66bd413bdc"><td class="memItemLeft" align="right" valign="top">localparam int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a3609a21c67a3c1b8ffe65c66bd413bdc">AXI_SEQ_ITEM_AW_NUM_BITS</a> = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__aw__vector__s">axi_seq_item_aw_vector_s</a>)</td></tr>
<tr class="separator:a3609a21c67a3c1b8ffe65c66bd413bdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abcfb4d0ea71d9d468d8d8ee492acdcc7"><td class="memItemLeft" align="right" valign="top">localparam int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#abcfb4d0ea71d9d468d8d8ee492acdcc7">AXI_SEQ_ITEM_W_NUM_BITS</a> = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__w__vector__s">axi_seq_item_w_vector_s</a>)</td></tr>
<tr class="separator:abcfb4d0ea71d9d468d8d8ee492acdcc7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a39ab1b1c2a814941adb3f0ceeef4b2aa"><td class="memItemLeft" align="right" valign="top">localparam int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a39ab1b1c2a814941adb3f0ceeef4b2aa">AXI_SEQ_ITEM_B_NUM_BITS</a> = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__b__vector__s">axi_seq_item_b_vector_s</a>)</td></tr>
<tr class="separator:a39ab1b1c2a814941adb3f0ceeef4b2aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8976bdc123c77c1eb4afc1e8f127c53"><td class="memItemLeft" align="right" valign="top">localparam int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#aa8976bdc123c77c1eb4afc1e8f127c53">AXI_SEQ_ITEM_AR_NUM_BITS</a> = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__ar__vector__s">axi_seq_item_ar_vector_s</a>)</td></tr>
<tr class="separator:aa8976bdc123c77c1eb4afc1e8f127c53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5ca03583008df77c259a2f1503fb3e9c"><td class="memItemLeft" align="right" valign="top">localparam int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="axi__pkg_8sv.html#a5ca03583008df77c259a2f1503fb3e9c">AXI_SEQ_ITEM_R_NUM_BITS</a> = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__r__vector__s">axi_seq_item_r_vector_s</a>)</td></tr>
<tr class="separator:a5ca03583008df77c259a2f1503fb3e9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<hr/><h2 class="groupheader">Class Documentation</h2>
<a name="structaxi__seq__item__aw__vector__s" id="structaxi__seq__item__aw__vector__s"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct axi_seq_item_aw_vector_s</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>This packed struct is used to send write address channel information between the DUT and TB. </p>
<p>Packed structs are emulator friendly </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00113">113</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>
</div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a148456644b1b5a6f5a7e655ec6191685"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
awaddr</td>
<td class="fielddoc">
<p>Starting burst address </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a52a86539de9462127b4d145af1cea8b9"></a>logic&lt; 1:0 &gt;</td>
<td class="fieldname">
awburst</td>
<td class="fielddoc">
<p>address burst mode. fixed, incrementing, or wrap </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a63e06f84b2a25d7e83125f159c923435"></a>logic&lt; 3:0 &gt;</td>
<td class="fieldname">
awcache</td>
<td class="fielddoc">
<p>Memory type. See AXI spec Memory Type A4-65 </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a0cc91e33e2158ce184451d71976513a5"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
awid</td>
<td class="fielddoc">
<p>Write address ID tag - A matching write response ID, bid, will be expected </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a92d3254b64f00ab0c9048b5fe5ebc78e"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#ab7eed2ef1c0b3f2e73a3ebe25df4b9e6">C_AXI_LEN_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
awlen</td>
<td class="fielddoc">
<p>Length, in beats/clks, of the matching write data burst </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ae3bc50eebd3f709e301b219eae36dcfc"></a>logic&lt; 0:0 &gt;</td>
<td class="fieldname">
awlock</td>
<td class="fielddoc">
<p>Used for locked transactions in AXI3 </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a4827dd3c5400e9a65008363b7a20c2f9"></a>logic&lt; 2:0 &gt;</td>
<td class="fieldname">
awprot</td>
<td class="fielddoc">
<p>Protected transaction. AXI4 only </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a2a2d278a013cc94ae98faba3c6658c7a"></a>logic&lt; 3:0 &gt;</td>
<td class="fieldname">
awqos</td>
<td class="fielddoc">
<p>Quality of service. AXI4 only </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a6a83a016049b05030b51a0acd20bce2b"></a>logic</td>
<td class="fieldname">
awready</td>
<td class="fielddoc">
<p>Slave is ready to receive write address channel information </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a738134782f1fba96b7cdfbadd38bae0c"></a>logic&lt; 2:0 &gt;</td>
<td class="fieldname">
awsize</td>
<td class="fielddoc">
<p>beat size. How many bytes wide are the beats in the write data transfer </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="aa65fb80d805c2a427b60e026dab1e297"></a>logic</td>
<td class="fieldname">
awvalid</td>
<td class="fielddoc">
<p>Values on write address channel are valid and won't change until awready is recieved </p>
</td></tr>
</table>

</div>
</div>
<a name="structaxi__seq__item__w__vector__s" id="structaxi__seq__item__w__vector__s"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct axi_seq_item_w_vector_s</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>This packed struct is used to send write data channel information between the DUT and TB. </p>
<p>Packed structs are emulator friendly </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00141">141</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>
</div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a1c277389685d707b62ef4973a6f2de65"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a3640be56d79c0ba42bea37784ac9ae6d">C_AXI_DATA_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
wdata</td>
<td class="fielddoc">
<p>Write Data </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a04ae983fcabaaba20311ef1004d4936f"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
wid</td>
<td class="fielddoc">
<p>Write ID tag. AXI3 only </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="af5659acbf2381fdadf5f02d5a37b8827"></a>logic</td>
<td class="fieldname">
wlast</td>
<td class="fielddoc">
<p>Write last. Indicates last beat in a write burst. </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ab0c07a62a0d7f3b7678b42d6024271ca"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a3640be56d79c0ba42bea37784ac9ae6d">C_AXI_DATA_WIDTH</a>/8-1:0 &gt;</td>
<td class="fieldname">
wstrb</td>
<td class="fielddoc">
<p>Write strobe. Indicates which byte lanes hold valid data. </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a7ade4559b2878314a715082945693990"></a>logic</td>
<td class="fieldname">
wvalid</td>
<td class="fielddoc">
<p>Write valid. Values on write data channel are valid and won't change until wready is recieved </p>
</td></tr>
</table>

</div>
</div>
<a name="structaxi__seq__item__b__vector__s" id="structaxi__seq__item__b__vector__s"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct axi_seq_item_b_vector_s</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>This packed struct is used to send write response channel information between the DUT and TB. </p>
<p>Packed structs are emulator friendly </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00162">162</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>
</div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a1037aca20e9a00c0867e3d703afbdfbe"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
bid</td>
<td class="fielddoc">
<p>Write Response ID tag </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ad9cdaf47fa03c7b15311a5315a615ca0"></a>logic&lt; 1:0 &gt;</td>
<td class="fieldname">
bresp</td>
<td class="fielddoc">
<p>Write Response.Indicates status of the write data transaction. </p>
</td></tr>
</table>

</div>
</div>
<a name="structaxi__seq__item__ar__vector__s" id="structaxi__seq__item__ar__vector__s"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct axi_seq_item_ar_vector_s</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>This packed struct is used to send read address channel information between the DUT and TB. </p>
<p>Packed structs are emulator friendly </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00178">178</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>
</div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a278863580e2abb564dbe11a0b3d13537"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
araddr</td>
<td class="fielddoc">
<p>Starting burst address </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="af22d24b86ec764b1dd184407ca7fdeee"></a>logic&lt; 1:0 &gt;</td>
<td class="fieldname">
arburst</td>
<td class="fielddoc">
<p>address burst mode. fixed, incrementing, or wrap </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a28bda75ceeaebee6b5caaeda4a2c3dc2"></a>logic&lt; 3:0 &gt;</td>
<td class="fieldname">
arcache</td>
<td class="fielddoc">
<p>Memory type. See AXI spec Memory Type A4-65 </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="af8f8bad97d8cf822e7f752472cc41e4c"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
arid</td>
<td class="fielddoc">
<p>Read address ID tag - A matching read data ID, rid, will be expected </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a80bce5e6e44526ab71f77a15fb47e8bd"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#ab7eed2ef1c0b3f2e73a3ebe25df4b9e6">C_AXI_LEN_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
arlen</td>
<td class="fielddoc">
<p>Length, in beats/clks, of the matching read data burst </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a8e67f1b24b60d2326f8548ab97f0cf82"></a>logic&lt; 0:0 &gt;</td>
<td class="fieldname">
arlock</td>
<td class="fielddoc">
<p>Used for locked transactions in AXI3 </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ae081d1a988271ce876f48b9d59e88dd6"></a>logic&lt; 2:0 &gt;</td>
<td class="fieldname">
arprot</td>
<td class="fielddoc">
<p>Protected transaction. AXI4 only </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a91d02129840239b4ab7da03d9e77bf67"></a>logic&lt; 3:0 &gt;</td>
<td class="fieldname">
arqos</td>
<td class="fielddoc">
<p>Quality of service. AXI4 only </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="ac7feaab83ae6741e9b3f4f7cf32081b5"></a>logic</td>
<td class="fieldname">
arready</td>
<td class="fielddoc">
<p>Slave is ready to receive read address channel information </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a781cfe20b63e690cdd11baad7b7951ca"></a>logic&lt; 2:0 &gt;</td>
<td class="fieldname">
arsize</td>
<td class="fielddoc">
<p>beat size. How many bytes wide are the beats in the write data transfer </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a65bec91195efa3bab89a7615046520f2"></a>logic</td>
<td class="fieldname">
arvalid</td>
<td class="fielddoc">
<p>Values on read address channel are valid and won't change until arready is recieved </p>
</td></tr>
</table>

</div>
</div>
<a name="structaxi__seq__item__r__vector__s" id="structaxi__seq__item__r__vector__s"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct axi_seq_item_r_vector_s</td>
        </tr>
      </table>
</div><div class="memdoc">
<div class="textblock"><p>This packed struct is used to send read data channel information between the DUT and TB. </p>
<p>Packed structs are emulator friendly </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00205">205</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>
</div><table class="fieldtable">
<tr><th colspan="3">Class Members</th></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a95251143daf1829f1de5f56203bfe3c1"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a3640be56d79c0ba42bea37784ac9ae6d">C_AXI_DATA_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
rdata</td>
<td class="fielddoc">
<p>Write Data </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a457f5a9657e6cdaf990763788401a26e"></a>logic&lt; <a class="el" href="axi__pkg_8sv.html#a150391b59e1b2851c89272c84ed02077">C_AXI_ID_WIDTH</a>-1:0 &gt;</td>
<td class="fieldname">
rid</td>
<td class="fielddoc">
<p>Read ID tag. </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="abafa44e60a310788057f90db49260cd3"></a>logic</td>
<td class="fieldname">
rlast</td>
<td class="fielddoc">
<p>Read last. Indicates last beat in a read burst. </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a1c71b6fec000f98430fd665d6c7d94a0"></a>logic&lt; 1:0 &gt;</td>
<td class="fieldname">
rresp</td>
<td class="fielddoc">
<p>Read Response.Indicates status of the read data transfer (of the same beat). </p>
</td></tr>
<tr><td class="fieldtype">
<a class="anchor" id="a3c649f7bfe7fcc3d23c4aae81777ee3d"></a>logic</td>
<td class="fieldname">
rvalid</td>
<td class="fielddoc">
<p>Write valid. Values on read data channel are valid and won't change until rready is recieved </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Typedef Documentation</h2>
<a class="anchor" id="a312fd2db42dcfe2d4cadc9b7175357f0"></a>
<div class="memitem">
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          <td class="memname">typedef bit&lt;<a class="el" href="axi__pkg_8sv.html#aa8976bdc123c77c1eb4afc1e8f127c53">AXI_SEQ_ITEM_AR_NUM_BITS</a>-1:0&gt; <a class="el" href="axi__pkg_8sv.html#a312fd2db42dcfe2d4cadc9b7175357f0">axi_seq_item_ar_vector_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit vector containing packed read address channel values. </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00197">197</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

</div>
</div>
<a class="anchor" id="a4c2433056567c2f85987e6a18fef7269"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">typedef bit&lt;<a class="el" href="axi__pkg_8sv.html#a3609a21c67a3c1b8ffe65c66bd413bdc">AXI_SEQ_ITEM_AW_NUM_BITS</a>-1:0&gt; <a class="el" href="axi__pkg_8sv.html#a4c2433056567c2f85987e6a18fef7269">axi_seq_item_aw_vector_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit vector containing packed write address channel values. </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00132">132</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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</div>
<a class="anchor" id="a4622f8d1c44a8bc0dd6e8eea04dfcfbb"></a>
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">typedef bit&lt;<a class="el" href="axi__pkg_8sv.html#a39ab1b1c2a814941adb3f0ceeef4b2aa">AXI_SEQ_ITEM_B_NUM_BITS</a>-1:0&gt; <a class="el" href="axi__pkg_8sv.html#a4622f8d1c44a8bc0dd6e8eea04dfcfbb">axi_seq_item_b_vector_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit vector containing packed write response channel values. </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00171">171</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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</div>
<a class="anchor" id="a6ff9a9241c4f3bc3a934bdd6c967107f"></a>
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">typedef bit&lt;<a class="el" href="axi__pkg_8sv.html#a5ca03583008df77c259a2f1503fb3e9c">AXI_SEQ_ITEM_R_NUM_BITS</a>-1:0&gt; <a class="el" href="axi__pkg_8sv.html#a6ff9a9241c4f3bc3a934bdd6c967107f">axi_seq_item_r_vector_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit vector containing packed read data channel values. </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00218">218</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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</div>
<a class="anchor" id="adde7476f486c8cdd6acc0bb33ef1ea70"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">typedef bit&lt;<a class="el" href="axi__pkg_8sv.html#abcfb4d0ea71d9d468d8d8ee492acdcc7">AXI_SEQ_ITEM_W_NUM_BITS</a>-1:0&gt; <a class="el" href="axi__pkg_8sv.html#adde7476f486c8cdd6acc0bb33ef1ea70">axi_seq_item_w_vector_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bit vector containing packed write data channel values. </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00154">154</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">enum <a class="el" href="axi__pkg_8sv.html#a80eb2d0d4b7978e716989546b93fa848">burst_size_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Size of beat in bytes. (How many bytes of the data bus are used each beat(clk). </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a35e86b0e0f722377718cfd9758cc8deb"></a>e_1BYTE&#160;</td><td class="fielddoc">
<p>Transfer 1 byte per beat (regardless of bus width) </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a3b71b0b1775203dd26093fab08eab521"></a>e_2BYTES&#160;</td><td class="fielddoc">
<p>Transfer 2 bytes per beat (regardles of bus width). Bus must be at least 2-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a01afde8339a75426fad830f0962f10e5"></a>e_4BYTES&#160;</td><td class="fielddoc">
<p>Transfer 4 bytes per beat (regardles of bus width). Bus must be at least 4-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a7b0e2780221101a2de9ed044008e6e96"></a>e_8BYTES&#160;</td><td class="fielddoc">
<p>Transfer 8 bytes per beat (regardles of bus width). Bus must be at least 8-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a98f7ccdf3d33a3e5a07253878d977d83"></a>e_16BYTES&#160;</td><td class="fielddoc">
<p>Transfer 16 bytes per beat (regardles of bus width). Bus must be at least 16-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a9abb5c28cb0c40e8845d6470b4e3657c"></a>e_32BYTES&#160;</td><td class="fielddoc">
<p>Transfer 32 bytes per beat (regardles of bus width). Bus must be at least 32-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a7abf5855cf6f1865568a9384c9fbe219"></a>e_64BYTES&#160;</td><td class="fielddoc">
<p>Transfer 64 bytes per beat (regardles of bus width). Bus must be at least 64-bytes wide </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="a80eb2d0d4b7978e716989546b93fa848a47e5b2d6b5341c90d3f172d47594f294"></a>e_128BYTES&#160;</td><td class="fielddoc">
<p>Transfer 128 bytes per beat (regardles of bus width). Bus must be at least 128-bytes wide </p>
</td></tr>
</table>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00076">76</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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</div>
<a class="anchor" id="ac948ddb69d517d21ce13ec363f10b95b"></a>
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          <td class="memname">enum <a class="el" href="axi__pkg_8sv.html#ac948ddb69d517d21ce13ec363f10b95b">burst_type_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Does the address stay fixed, increment, or wrap during the burst? </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="ac948ddb69d517d21ce13ec363f10b95ba7759f7b1845ad2e729ccf878ff1b2e40"></a>e_FIXED&#160;</td><td class="fielddoc">
<p>The address doesn't change during the burst. Example: burstin to fifo </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac948ddb69d517d21ce13ec363f10b95ba66585ba1c5e2c6e635898a45086d9c1d"></a>e_INCR&#160;</td><td class="fielddoc">
<p>The address increments during the burst. Example: bursting to memmory </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac948ddb69d517d21ce13ec363f10b95bac6caff421238a869ca419bbd19325b8c"></a>e_WRAP&#160;</td><td class="fielddoc">
<p>The address wraps to a lower address once it hits the higher address. Refer to AXI Spec section A3.4.1 for details. Example: cache line accesses </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac948ddb69d517d21ce13ec363f10b95ba4375ed062d322ec2c9581b61f2b6b689"></a>e_RESERVED&#160;</td><td class="fielddoc">
</td></tr>
</table>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00089">89</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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<a class="anchor" id="ac8b0f779dd7c96753c4355a5c86e0f9d"></a>
<div class="memitem">
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          <td class="memname">enum <a class="el" href="axi__pkg_8sv.html#ac8b0f779dd7c96753c4355a5c86e0f9d">response_type_t</a></td>
        </tr>
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<p>Write response values. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a class="anchor" id="ac8b0f779dd7c96753c4355a5c86e0f9da01e497eaf63b1bf53a0105479c8c74de"></a>e_OKAY&#160;</td><td class="fielddoc">
<p>Normal access success. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac8b0f779dd7c96753c4355a5c86e0f9dad43dac468b1bc25183dd4e26a504bc3a"></a>e_EXOKAY&#160;</td><td class="fielddoc">
<p>Exlusive access okay. </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac8b0f779dd7c96753c4355a5c86e0f9da1fe56b6c3532c9dbf95cd6ceb8e6b280"></a>e_SLVERR&#160;</td><td class="fielddoc">
<p>Slave error. Slave received data successfully but wants to return error condition </p>
</td></tr>
<tr><td class="fieldname"><a class="anchor" id="ac8b0f779dd7c96753c4355a5c86e0f9dafdc0186d85ac39b36e66dab544b906c3"></a>e_DECERR&#160;</td><td class="fielddoc">
<p>Decode error. Generated typically by interconnect to signify no slave at that address </p>
</td></tr>
</table>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00098">98</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="afbfbf7a50bf6dabae3804e39d05434b1"></a>
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          <td class="memname">bit&lt;<a class="el" href="axi__pkg_8sv.html#ab7eed2ef1c0b3f2e73a3ebe25df4b9e6">C_AXI_LEN_WIDTH</a>-1:0&gt; calculate_axlen </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 2:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input shortint&#160;</td>
          <td class="paramname"><em>burst_length</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>calculate awlen or arlen </p>
<p>Calculate the number of beats -1 for a burst. Subtract one because awlen and arlen are one less than the transfer count. awlen=0, means 1 beat. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
    <tr><td class="paramname">burst_length</td><td>- how many bytes long is the burst </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the burst_size aligned address </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00320">320</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00065">C_AXI_LEN_WIDTH</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00374">calculate_unalignment_offset()</a>.</p>

<p>Referenced by <a class="el" href="axi__uvm__pkg_8sv_source.html#l00193">ar_from_class()</a>, <a class="el" href="axi__uvm__pkg_8sv_source.html#l00094">aw_from_class()</a>, <a class="el" href="axi__sequential__reads__seq_8svh_source.html#l00064">axi_sequential_reads_seq::body()</a>, <a class="el" href="axi__pipelined__reads__seq_8svh_source.html#l00140">axi_pipelined_reads_seq::body()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00406">calculate_wrap_boundary()</a>, <a class="el" href="axi__seq__item_8svh_source.html#l00492">axi_seq_item::get_beat_N_data()</a>, <a class="el" href="axi__monitor_8svh_source.html#l00316">axi_monitor::read_address()</a>, <a class="el" href="axi__driver_8svh_source.html#l00605">axi_driver::read_data()</a>, <a class="el" href="axi__responder_8svh_source.html#l00288">axi_responder::read_data()</a>, <a class="el" href="memory_8svh_source.html#l00085">memory::seq_item_check()</a>, and <a class="el" href="axi__driver_8svh_source.html#l00233">axi_driver::write_data()</a>.</p>

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          <td class="memname">bit&lt;<a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0&gt; calculate_burst_aligned_address </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>address</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 2:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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</div><div class="memdoc">

<p>calculate burst_size aligned address </p>
<p>The AXI function to calculate aligned address is: Aligned_Address = (Address/(2**burst_size)*(2**burst_size) Zeroing out the bottom burst_size bits does the same thing which is much more eaily synthesizable. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">address</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the burst_size aligned address </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00230">230</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00059">C_AXI_ADDR_WIDTH</a>, <a class="el" href="axi__pkg_8sv_source.html#l00083">e_128BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00080">e_16BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00076">e_1BYTE</a>, <a class="el" href="axi__pkg_8sv_source.html#l00077">e_2BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00081">e_32BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00078">e_4BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00082">e_64BYTES</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00079">e_8BYTES</a>.</p>

<p>Referenced by <a class="el" href="axi__uvm__pkg_8sv_source.html#l00193">ar_from_class()</a>, <a class="el" href="axi__uvm__pkg_8sv_source.html#l00094">aw_from_class()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00406">calculate_wrap_boundary()</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00538">get_beat_N_byte_lanes()</a>.</p>

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          <td class="memname">bit&lt;<a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0&gt; calculate_bus_aligned_address </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>bus_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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</div><div class="memdoc">

<p>calculate bus-siz aligned address </p>
<p>The AXI function to calculate aligned address is: Aligned_Address = (Address/(2**bus_size)*(2**bus_sze) Zeroing out the bottom burst_size bits does the same thing which is much more eaily synthesizable. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">bus_size</td><td>- how many bytes wide is the bus </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the bus_size aligned address </dd></dl>
<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000001">Todo:</a></b></dt><dd>: bus_size could be byte instead of int? </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00272">272</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00059">C_AXI_ADDR_WIDTH</a>, <a class="el" href="axi__pkg_8sv_source.html#l00083">e_128BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00080">e_16BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00076">e_1BYTE</a>, <a class="el" href="axi__pkg_8sv_source.html#l00077">e_2BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00081">e_32BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00078">e_4BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00082">e_64BYTES</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00079">e_8BYTES</a>.</p>

<p>Referenced by <a class="el" href="axi__pkg_8sv_source.html#l00538">get_beat_N_byte_lanes()</a>.</p>

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          <td class="memname">byte calculate_unalignment_offset </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input byte&#160;</td>
          <td class="paramname"><em>burst_size</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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<p>calculate how unaligned the address is from the burst size </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>how many bytes the address is unaligned from the burst_size </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00374">374</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00083">e_128BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00080">e_16BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00076">e_1BYTE</a>, <a class="el" href="axi__pkg_8sv_source.html#l00077">e_2BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00081">e_32BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00078">e_4BYTES</a>, <a class="el" href="axi__pkg_8sv_source.html#l00082">e_64BYTES</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00079">e_8BYTES</a>.</p>

<p>Referenced by <a class="el" href="axi__pkg_8sv_source.html#l00320">calculate_axlen()</a>.</p>

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</p>

</div>
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<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void calculate_wrap_boundary </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 2:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input shortint&#160;</td>
          <td class="paramname"><em>burst_length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">output bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>Lower_Wrap_Boundary</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">output bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>Upper_Wrap_Boundary</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>calculate the wrap boundaries for a given burst </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
    <tr><td class="paramname">burst_length</td><td>- how many bytes is the burst </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Lower_Wrap_Boundary - Lower Wrap Boundary Address </dd>
<dd>
Upper_Wrap_Boundary - Upper Wrap Boundary Address </dd></dl>
<dl class="todo"><dt><b><a class="el" href="todo.html#_todo000002">Todo:</a></b></dt><dd>: simplify the logic needed for the math in this function </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00406">406</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00059">C_AXI_ADDR_WIDTH</a>, <a class="el" href="axi__pkg_8sv_source.html#l00320">calculate_axlen()</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00230">calculate_burst_aligned_address()</a>.</p>

<p>Referenced by <a class="el" href="axi__pkg_8sv_source.html#l00447">get_next_address()</a>.</p>

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<a class="anchor" id="a269e42497226a3a0def0fc1bfdd7d22a"></a>
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        <tr>
          <td class="memname">void get_beat_N_byte_lanes </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 2:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input shortint&#160;</td>
          <td class="paramname"><em>burst_length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 1:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_type</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>beat_cnt</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>data_bus_bytes</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">output int&#160;</td>
          <td class="paramname"><em>Lower_Byte_Lane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">output int&#160;</td>
          <td class="paramname"><em>Upper_Byte_Lane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">output int&#160;</td>
          <td class="paramname"><em>offset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>return byte lanes that contain valid data </p>
<p>given the beat number and how wide the bus is, return which lanes to get data from and also what offset from start address to write to.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
    <tr><td class="paramname">burst_length</td><td>- how many bytes is the burst </td></tr>
    <tr><td class="paramname">burst_type</td><td>- Fixed, Incrementing or Wrap </td></tr>
    <tr><td class="paramname">beat_cnt</td><td>which beat in the burst, starting at 0. </td></tr>
    <tr><td class="paramname">data_bus_bytes</td><td>- how wide is the bus (the driver/responder can get this from the interface </td></tr>
    <tr><td class="paramname">Lower_Byte_Lane</td><td>- Lower valid byte lane </td></tr>
    <tr><td class="paramname">Upper_Byte_Lane</td><td>- Upper valid byte lane </td></tr>
    <tr><td class="paramname">offset</td><td>- offset from Start_Address. Can be used to write to memory. </td></tr>
  </table>
  </dd>
</dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00538">538</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00230">calculate_burst_aligned_address()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00272">calculate_bus_aligned_address()</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00089">e_FIXED</a>.</p>

<p>Referenced by <a class="el" href="axi__seq__item_8svh_source.html#l00492">axi_seq_item::get_beat_N_data()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00447">get_next_address()</a>, <a class="el" href="axi__monitor_8svh_source.html#l00316">axi_monitor::read_address()</a>, <a class="el" href="axi__driver_8svh_source.html#l00605">axi_driver::read_data()</a>, and <a class="el" href="axi__monitor_8svh_source.html#l00169">axi_monitor::write_data()</a>.</p>

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          <td class="memname">bit&lt;<a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0&gt; get_next_address </td>
          <td>(</td>
          <td class="paramtype">input bit&lt; <a class="el" href="axi__pkg_8sv.html#ab3a4347d855f294afac6e48ad076f677">C_AXI_ADDR_WIDTH</a>-1:0 &gt;&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 2:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_size</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input shortint&#160;</td>
          <td class="paramname"><em>burst_length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input bit&lt; 1:0 &gt;&#160;</td>
          <td class="paramname"><em>burst_type</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>beat_cnt</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>lane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">input int&#160;</td>
          <td class="paramname"><em>data_bus_bytes</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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</div><div class="memdoc">

<p>Get next address for reading/writing to memory. </p>
<p>Takes into account burst_type. IE: e_FIXED, e_INCR, e_WRAP This function is stateful. When called it updates an internal variable that holds the current address. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">addr</td><td>- starting address </td></tr>
    <tr><td class="paramname">burst_size</td><td>- how many bytes wide is the beat </td></tr>
    <tr><td class="paramname">burst_length</td><td>- how many bytes is the burst </td></tr>
    <tr><td class="paramname">burst_type</td><td>- Fixed, Incrementing or Wrap </td></tr>
    <tr><td class="paramname">beat_cnt</td><td>- beat count the memory address corresponds to. Used with lane. </td></tr>
    <tr><td class="paramname">lane</td><td>- lane thememory address correspons to. Usedwith beat_cnt </td></tr>
    <tr><td class="paramname">data_bus_bytes</td><td>- how wide is the bus? </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>memory address that corresponds to the addr + beat_cnt/lane byte </dd></dl>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00447">447</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>References <a class="el" href="axi__pkg_8sv_source.html#l00059">C_AXI_ADDR_WIDTH</a>, <a class="el" href="axi__pkg_8sv_source.html#l00406">calculate_wrap_boundary()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00089">e_FIXED</a>, <a class="el" href="axi__pkg_8sv_source.html#l00090">e_INCR</a>, <a class="el" href="axi__pkg_8sv_source.html#l00091">e_WRAP</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00538">get_beat_N_byte_lanes()</a>.</p>

<p>Referenced by <a class="el" href="axi__monitor_8svh_source.html#l00316">axi_monitor::read_address()</a>, and <a class="el" href="axi__monitor_8svh_source.html#l00169">axi_monitor::write_data()</a>.</p>

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<h2 class="groupheader">Variable Documentation</h2>
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          <td class="memname">localparam int AXI_SEQ_ITEM_AR_NUM_BITS = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__ar__vector__s">axi_seq_item_ar_vector_s</a>)</td>
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<p>Used to calculate the length of the bit vector containing the packed read address struct </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00193">193</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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          <td class="memname">localparam int AXI_SEQ_ITEM_AW_NUM_BITS = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__aw__vector__s">axi_seq_item_aw_vector_s</a>)</td>
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<p>Used to calculate the length of the bit vector containing the packed write address struct </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00128">128</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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          <td class="memname">localparam int AXI_SEQ_ITEM_B_NUM_BITS = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__b__vector__s">axi_seq_item_b_vector_s</a>)</td>
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<p>Used to calculate the length of the bit vector containing the packed write response struct </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00167">167</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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          <td class="memname">localparam int AXI_SEQ_ITEM_R_NUM_BITS = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__r__vector__s">axi_seq_item_r_vector_s</a>)</td>
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<p>Used to calculate the length of the bit vector containing the packed read data struct </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00214">214</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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          <td class="memname">localparam int AXI_SEQ_ITEM_W_NUM_BITS = $bits(<a class="el" href="axi__pkg_8sv.html#structaxi__seq__item__w__vector__s">axi_seq_item_w_vector_s</a>)</td>
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<p>Used to calculate the length of the bit vector containing the packed write data struct </p>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00150">150</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

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          <td class="memname">parameter C_AXI_ADDR_WIDTH = <a class="el" href="params__pkg_8sv.html#a243e565e7e0e8614253648f1c4c47a2a">params_pkg::AXI_ADDR_WIDTH</a></td>
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<p>bit width of address bus. Valid values:</p><ul>
<li>32</li>
<li>64 </li>
</ul>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00059">59</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>Referenced by <a class="el" href="axi__if_8sv_source.html#l00039">axi_if()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00230">calculate_burst_aligned_address()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00272">calculate_bus_aligned_address()</a>, <a class="el" href="axi__pkg_8sv_source.html#l00406">calculate_wrap_boundary()</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00447">get_next_address()</a>.</p>

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          <td class="memname">parameter C_AXI_DATA_WIDTH = <a class="el" href="params__pkg_8sv.html#aefb87aba63546102696230c367fae534">params_pkg::AXI_DATA_WIDTH</a></td>
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<p>bit width of data bus. Valid values:</p><ul>
<li>8</li>
<li>16</li>
<li>32</li>
<li>64</li>
<li>128</li>
<li>256</li>
<li>512</li>
<li>1024 </li>
</ul>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00048">48</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>Referenced by <a class="el" href="axi__if_8sv_source.html#l00039">axi_if()</a>.</p>

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          <td class="memname">parameter C_AXI_ID_WIDTH = <a class="el" href="params__pkg_8sv.html#acc3f1524ce307037059dc1777798ee1f">params_pkg::AXI_ID_WIDTH</a></td>
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<p>bit width of the ID fields</p><ul>
<li>awid</li>
<li>wid [AXI3]</li>
<li>bid</li>
<li>arid</li>
<li>rid </li>
</ul>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00041">41</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>Referenced by <a class="el" href="axi__if_8sv_source.html#l00039">axi_if()</a>.</p>

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          <td class="memname">parameter C_AXI_LEN_WIDTH = <a class="el" href="params__pkg_8sv.html#afd06121ba6ea9496041ee05853712a73">params_pkg::AXI_LEN_WIDTH</a></td>
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<p>bit width of awlen and arlen bus. Valid values:</p><ul>
<li>4 - AXI3</li>
<li>8 - AXI4 (burst_type=e_INCR) </li>
</ul>

<p>Definition at line <a class="el" href="axi__pkg_8sv_source.html#l00065">65</a> of file <a class="el" href="axi__pkg_8sv_source.html">axi_pkg.sv</a>.</p>

<p>Referenced by <a class="el" href="axi__if_8sv_source.html#l00039">axi_if()</a>, and <a class="el" href="axi__pkg_8sv_source.html#l00320">calculate_axlen()</a>.</p>

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